Transposition Mechanism for Sparse Matrices on Vector Processors

Many scientific applications involve operations on sparse matrices. However, due to irregularities induced by the sparsity patterns, many operations on sparse matrices execute inefficiently on traditional scalar and vector architectures. To tackle this problem a scheme has been proposed consisting of two parts: (a) An extension to a vector architecture to support sparse matrix-vector multiplication using (b) a novel Blocked Based sparse matrix Compression Storage (BBCS) format. Within this context, in this paper we propose and describe a hardware mechanism for the extended vector architecture that performs the transposition AT of a sparse matrix A using a hierarchical variation of the aforementioned sparse matrix compression format. The proposed Sparse matrix Transposition Mechanism (STM) is used as a Functional Unit for a vector processor and requires an s s word in-processor memory where s is the vector processor’s section size. In this paper we provide a full description of the STM and show an expected performance increase of one order of magnitude. Keywords— Vector processor, matrix transpose, sparse matrix, functional unit